The present invention relates generally to the fabrication of integrated circuits (IC""s), and more particularly to the fabrication of memory IC""s.
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones, for example. One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor is a dynamic random access memory (DRAM). A DRAM typically includes millions or billions of individual DRAM cells, with each cell storing one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
Another memory semiconductor device is called a ferroelectric random access memory (FRAM). An FRAM typically has a similar structure to a DRAM but is comprised of materials such that the storage capacitor does not need to be refreshed continuously as in a DRAM. Common applications for FRAM""s include cellular phones and digital cameras, for example.
The semiconductor industry in general is being driven to decrease the size of semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today""s semiconductor products. A challenge in producing memory devices such as DRAM""s and FRAM""s is maintaining the minimum amount of charge that must be stored in a storage capacitor to obtain reliable operation of the memory device. One way to increase the capacitance density of memory devices is to use higher permittivity capacitance dielectric materials such as barium-strontium titanate (Ba,Sr)TiO3 (BSTO).
Shown in FIG. 1 is a cross-sectional view of a prior art DRAM stacked capacitor structure, with a storage capacitor 18 above a bit line contact 16 and connecting to underlying devices through polysilicon plugs 17. The capacitor structure 18 is built upon a substrate 12 which typically comprises polysilicon and may also include underlying semiconductor layers and structures. Word line 14 and bit line 16 provide an address array to enable the programming or charging, or reading of the capacitor 18 during use. Cell plate 28 overlies the high dielectric constant (k) material 26 which may comprise BSTO, for example. Bottom electrode 24 comprises platinum (Pt) overlying a conductive barrier layer 22. Pt is typically used because of its superior work function. The barrier layer 22 comprises a conductive material and is used to separate the electrode 24 from the plug material 20 to prevent electrode-plug interdiffusion and reaction. Barrier layer 22 also protects the plug 17 against oxygen exposure during the deposition of the BSTO dielectric 26, which typically occurs in a high temperature oxygen environment at temperatures in the range of 450 to 700xc2x0 C. The high dielectric constant material 26 conformally coats the bottom electrode 24, and the counter-electrode forms a plate 28 that is common to an array of a plurality of capacitors 18.
A problem with the stacked capacitor structure 18 using a high dielectric constant material 26 shown in FIG. 1 is that upon deposition of the high dielectric constant material 26, oxygen diffuses through the platinum of electrode 24 to barrier layer 22, forming an oxide layer 30 between bottom electrode 24 and conductive barrier layer 22. Oxide layer 30 comprises an interfacial low dielectric layer between electrode 24 and barrier layer 22 and is typically about 15 nm thick.
The formation of oxide layer 30 is problematic because the bottom electrode is required to be conductive. Oxide 30 typically comprises a non-conductive oxide such as such as TaSiNxOy, creating an open in the bottom electrode 24, or increasing the resistance of the bottom electrode 24. A similar oxide barrier layer may also form between Pt 24 and plug 17 during BSTO deposition if no barrier layer 22 is used.
What is needed in the art is a memory cell bottom electrode design and method of fabrication thereof that prevents the formation of a non-conductive oxide 30 within the bottom electrode.
In Japanese Patent No. 10-242078 entitled xe2x80x9cMulti-Layer Electrode Using Conductive Oxide,xe2x80x9d issued to Sharp Corporation and published on Sep. 11, 1998, a multi-layer electrode is proposed, in which a conductive barrier layer 122 is formed, and a layer of Iridium (Ir) 132 is deposited over barrier layer 122, as shown in FIG. 2. A relatively thick layer of Iridium oxide (IrO2) 134 is deposited over the Ir layer 132, as shown in FIG. 2. Pt electrode material 124 is deposited over the IrO2 layer 134.
While the Ir layer 132 and IrO2 layer 134 are conductive and inhibit oxygen diffusion to the poly silicon underneath the barrier liner 122, the structure shown in FIG. 2 is disadvantageous because the excessive thicknesses of the Ir layer 132 and IrO2 layer 134 do not permit the use of the same etchant gas as used to process the Pt material 124, for example. Therefore, several different etchant gases are required to pattern the electrode, requiring increased labor, time, and an increase in the number and variety of processing chemicals.
The present invention achieves technical advantages as a multi-layer platinum electrode for use in memory devices having high dielectric constant materials. A multi-layer electrode stack having a thin conductive oxide layer to control the electrode texture prevents oxygen diffusion through the electrode. The thin conductive oxide layer is etchable with the same gases used to etch the conductive electrode materials.
Disclosed is a multi-layer electrode for an integrated circuit, including a conductive barrier layer, a first conductive liner deposited over the conductive barrier layer, a second conductive liner deposited over the first conductive liner, and a conductive layer deposited over the second conductive liner, where the conductive layer and the first conductive liner comprise the same material.
Also disclosed is a multi-layer electrode for an integrated circuit, comprising a conductive barrier layer, a first conductive liner deposited over the conductive barrier layer, a second conductive liner comprising a conductive oxide deposited over the first conductive liner, and a conductive layer deposited over the second conductive liner.
Further disclosed is a method of fabricating an electrode of an integrated circuit, comprising depositing a conductive barrier layer over a substrate, depositing a first conductive liner over the conductive barrier layer, depositing a second conductive liner over the first conductive liner, and depositing a conductive layer over the second conductive liner, where the conductive layer and the first conductive liner comprise the same material.
Advantages of the invention include prohibiting oxygen diffusion through the multi-layer electrode to the barrier layer interface, preventing the formation of an oxide layer which can cause an open and increase the resistance of the electrode. Material variation is reduced during electrode patterning, for example, the same etchant gas may be used to pattern the conductive layer of the electrode and the first and second conductive liners. The method and structure described herein may be used and applied to a variety of memory integrated circuits, such as DRAM""s and FRAM""s. The columnar grain growth of Pt is stopped by the insertion of the conductive oxide layer between two Pt layers in accordance with the present invention.